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3.Challenges of high speed
Rising of the high-frequency and high speed, signal integrity is being a trouble to R & D, including driving capacity, and the reflection, crosstalk, overshoot, ring-back and attenuation etc. The simulation module Signoise in Allegro is based on IBIS model, and able to be easily used to build a topology for simulation.
The simulation tool in Allegro has a good interfaces with the routing platform. After the routing for is completed, the parameters on the PCB can be directly transfer to Signoise platform.
The layout constraint gotten by simulation can be directly sent into the electric-rule manager in Allegro which can constrain the Length matching rules. In the course of layout, if the length is not consistent with the specified rule, Allegro will give an real-time alarm. 
Drawing 2: Example for constrain manager
As shown in the above, if the length is within the specified range, the corresponding field in the table will turn green. If not, whether shorter or longer, the corresponding field in the table will becomes red.
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08-07-21
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